Cubic memory array

G - Physics – 11 – C

Patent

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Details

G11C 5/02 (2006.01) G11C 7/12 (2006.01) G11C 7/18 (2006.01) G11C 11/34 (2006.01) H01L 21/822 (2006.01) H01L 23/52 (2006.01) H01L 27/06 (2006.01) H01L 27/10 (2006.01) H01L 21/8239 (2006.01) H01L 27/105 (2006.01)

Patent

CA 2433112

A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.

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