G - Physics – 06 – F
Patent
G - Physics
06
F
354/204
G06F 7/50 (2006.01)
Patent
CA 1076706
5202599 ABSTRACT The invention comprises circuitry for providing a carry-save adder function. The circuit is responsive to three binary inputs corresponding to two addend bits and a carry bit and produces two output signals corresponding to a sum-bit and a carry-bit. The circuit is implemented using current mode logic in which two half-adders are concatenated to provide a carry-save adder. The gates within the circuit are series-coupled so as to require a minimum of space and power. -1-
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