G - Physics – 06 – F
Patent
G - Physics
06
F
354/233
G06F 15/16 (2006.01) G06F 13/12 (2006.01) G06F 13/28 (2006.01)
Patent
CA 1182577
CYCLE STEALING I/O CONTROLLER WITH PROGRAMMABLE OFFLINE MODE OF OPERATION Abstract A dual mode microprocessor acts either as a front-end I/O controller processor relative to a primary/ host processor and device or as a secondary data pro- cessor having independent storage, processing and I/O capabilities. Host software prepares device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor and evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a program- mable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, through a specified interface busing path and in a specified bit-parallel format. The adapters perform this transfer in an autonomous manner, i.e., without assistance from either processor. In PO mode the microprocessor directs associated elements to perform one or more programs of operations defined by secondary commands contained in a command list. Such lists, prepared in advance in host system memory, are trans- ferred to the microprocessor's memory by special PO mode "LOAD" type DCB's, and interpreted in response to special PO mode type "START" DCB's. A list transferred by one LOAD DCB may be repeatedly accessed at various positions by several START DCB's. The architecture of the command list includes commands which permit the microprocessor to exchange data with the host and/or a device, perform arithmetic operations on data, perform bit and byte manipulative operations on data, and directly control the device interface. PO mode se- quences are terminatable by the microprocessor in response to various internal and external conditions. Upon termination the microprocessor evokes either a DCB chaining action or a host system interruption for transferring concluding status, depending on the value of the chaining bit in the current (start type) DCB.
419296
Heath Chester A.
Van Duren Richard G.
International Business Machines Corporation
Rosen Arnold
LandOfFree
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