D.c. stable semiconductor memory cell

Details D.c. stable semiconductor memory cell D.c. stable semiconductor memory cell

G - Physics

11

C

352/82.3

G11C 7/02 (2006.01) G11C 11/24 (2006.01) G11C 11/40 (2006.01)

Patent

CA 1060994

D.C. STABLE SEMICONDUCTOR MEMORY CELL Abstract of the Disclosure Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's . The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

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