Darlington transistor arrangement

H - Electricity – 03 – F

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Details

330/15, 330/27

H03F 3/26 (2006.01) H03F 3/30 (2006.01) H03F 3/343 (2006.01)

Patent

CA 1223927

ABSTRACT Darlington transistor arrangement. The emitter of an input transistor (T1) of a Darlington transistor is connected to the base of an out- put transistor (T2). The collector of the input transis- tor (T1) is connected to the input of a current amplifier circuit comprising a third transistor (T3) arranged as a diode and having a first resistor (R1) arranged in its emitter circuit, and a fourth transistor (T4) having its base is connected to that of the third transistor (T3) and having a second resistor (R2) arranged in the emitter circuit. The collector of the fourth transistor (T4) is connected to the base of the output transistor (T2). The ratio between the resistance values of the first and the second resistors (R1, R2) is larger than the ratio be- tween the emitter areas of the fourth and the third tran- sistor (T4, T3). Thus, for small currents a low and for large currents a high current gain is obtained, so that the current gain factor of the output transistor (T2) which decreases for large currents is compensated for partly. Moreover, the base current of the input transis- tor (T1) remains small in the case of large output cur- rents. Fig. 2.

475080

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