Data access circuit for a memory array

Details Data access circuit for a memory array Data access circuit for a memory array

G - Physics

11

C

354/223, 354/237

G11C 29/00 (2006.01) G06F 3/16 (2006.01) G06F 5/00 (2006.01) G06F 11/00 (2006.01) G06F 11/10 (2006.01) G06F 12/02 (2006.01) G11C 7/00 (2006.01) G11C 8/04 (2006.01)

Patent

CA 1087740

DATA ACCESS CIRCUIT FOR A MEMORY ARRAY Abstract of the Disclosure A memory array, having a plurality of intersecting rows and columns, stores digitized speech. Each row and column intersection consists of a binary storage cell for storing one bit of digitized speech. Incoming digitized speech is loaded into columns of the memory array in a plurality of repetitive loading sequences, each loading sequence including; reading out the bits stored in success- ive rows of binary storage cells, replacing in each successive row of bits, a predetermined one of the bits in the read out row with a successive one of the bits of the digitized speech and writing each read out row of bits including the replaced bit back into the row. Multi- bit binary grunts (digitized speech segments) stored in the array are read out therefrom by applying the bits of the grunts to time slots in frames on a time-division highway, each frame being of n bits duration and including one bit from each of n grunts stored in the array. A selected grunt is extracted from the highway by commencing a count of the bits on the highway with a first bit of the selected grunt and by extracting the first bit and every nth bit thereafter. Memory malfunction is indicated when the number of rows in the array containing parity errors exceeds a predetermined threshold number.

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