G - Physics – 11 – C
Patent
G - Physics
11
C
354/105, 354/236
G11C 13/00 (2006.01) G06K 15/10 (2006.01) G11C 19/28 (2006.01)
Patent
CA 1122717
ABSTRACT Apparatus for assembling binary data bits in parallel by groups in variable, selected locations in a shift register for subsequent serial readout. One or more shift registers are arranged in a matrix of rows and columns of storage cells and addressed along one coordinate while a plurality of data are applied in parallel along the orthogonal. Selector circuits are controlled to selectively shift a data word to enable the first bit in the word to be stored in any storage position within the addressed coordinate, with each remaining bit in the word stored in a correspondingly contiguous storage position in the matrix. Bit storage cells of the shift registers are of the set-reset latch type so that once set they cannot be changed by subsequent data bits until the entire array is reset. This enables the overwriting of successive data bytes.
327403
Nosowicz Eugene J.
Pearson Robert C.
International Business Machines Corporation
Kerr Alexander
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