Data buffer retiming circuit

Details Data buffer retiming circuit Data buffer retiming circuit

H - Electricity

04

L

328/87

H04L 7/00 (2006.01) G06F 5/06 (2006.01) H04J 3/06 (2006.01)

Patent

CA 1090888

DATA BUFFER RETIMING CIRCUIT by Alvin L. Pachynski, Jr. ABSTRACT OF THE DISCLOSURE A data buffer retiming circuit makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state. -1-

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