Data bus fault detection circuit and method

Details Data bus fault detection circuit and method Data bus fault detection circuit and method

G - Physics

08

C

G08C 25/00 (2006.01) H03K 5/19 (2006.01) H04B 17/00 (2006.01) H04L 25/08 (2006.01)

Patent

CA 2409589

A receiver circuit is connected to a differential serial bus having first and second signal conductors. The receiver circuit includes a fault detection circuit which generates a difference signal representing a difference between a first signal on the first conductor and a second signal on the second conductors. A comparing circuit includes a plurality of comparators for comparing the difference signal, the first signal and the second signal to predetermined voltage levels. The comparing circuit also includes a plurality of logic units coupled to outputs of the comparators. A signal select circuit has a pair of inputs coupled to the first and second conductors, logic inputs coupled to logic outputs of the comparing circuit, and a signal output. The signal select circuit and the comparing circuit cooperate to control communication of the first and second conductors with the signal output as a function of fault conditions on the first and second conductors.

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