Data capture logic for vlsi chips

Details Data capture logic for vlsi chips Data capture logic for vlsi chips

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G01R 31/3185 (2006.01) G06F 11/22 (2006.01) G06F 11/34 (2006.01)

Patent

CA 1243353

Abstract of the Disclosure The present data capture logic system is placed into VLSI chip design as a test and error detection system over and above the data handling circuits necessary for the VLSI chip design. The system includes an input series of control regis- ters which receives control operands which determine which of a variety of possible functions are performed by the system. The control registers are connected with data capture registers associated only with the data capture logic system, multi- plexers, and capture mode select and delay logic circuits. The capture mode select and delay logic circuits are connected with the registers and multiplexers which are in turn connected with various components of the VLSI logic system and these circuits control which operands are inserted into the data capture logic registers and the time at which such operands are captured. The data capture logic registers are connected to an output register which holds all of the output data capture logic information in parallel. Various selection networks control which operands are put into the output register. At the appro- priate time signal, the data capture logic output operand is removed from the chip in serial fashion so that a minimal number of input and output pins are used. Various test functions may be performed by setting the control operands differently. Various operands from the VLSI logic may be captured at different times during operation of the VLSI chip by setting various control operands. The basic design of the logic allows capture of operand signals at different times. The capture time delay allows a logic analyzer report to be made for a loop-type test sequence.

492064

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