Data clock recovery circuit

Details Data clock recovery circuit Data clock recovery circuit

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/08 (2006.01) H04L 5/14 (2006.01) H04L 7/00 (2006.01) H03L 7/087 (2006.01) H03L 7/089 (2006.01)

Patent

CA 2173086

Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC). In the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation. To avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of which, which is added in an adder circuit (ADD) to that coming from the first loop, produces voltage pulses when both signals are not at the same frequency, provoking a non- locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

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