Data multiplexing device

H - Electricity – 04 – J

Patent

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363/10

H04J 3/02 (2006.01) H04J 3/04 (2006.01) H04J 3/06 (2006.01)

Patent

CA 2033142

-20- ABSTRACT OF THE DISCLOSURE In a high-speed data multiplexing device with a plurality of data multiplexing circuits there are included in each data multiplexing circuit a frequency divider for frequency dividing the same clock and a logic circuit for time division multiplexing input data of a plurality of channels in accordance with the output of the frequency divider. The outputs of the frequency dividers are subjected to a logical operation by a gate circuit. A voltage corresponding to the duty ratio of the operated output from the gate circuit is compared with a reference voltage in a detector/controller section. It is determined, based on the result of comparison, whether or not the frequency dividing phases of the frequency dividers of the data multiplexing circuits are uniform, and if not, a reset signal is applied to the frequency dividers to reset them to thereby make their frequency dividing phases uniform.

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