G - Physics – 06 – F
Patent
G - Physics
06
F
354/246
G06F 12/08 (2006.01) G05B 19/05 (2006.01) G06F 12/06 (2006.01) G06F 11/10 (2006.01)
Patent
CA 1168377
ABSTRACT OF THE DISCLOSURE A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decod- ing macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro- instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory stor- age using eight storage segments (rings), access to the rings being con- trolled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
376127
Druke Michael B.
Ziegler Michael L.
Data General Corporation
Smart & Biggar
LandOfFree
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