G - Physics – 06 – F
Patent
G - Physics
06
F
354/234
G06F 13/36 (2006.01) G06F 13/374 (2006.01)
Patent
CA 1313414
A DATA PROCESSING SYSTEM HAVING A SHARED BUS AND A PRIORITY DETERMINATION CIRCUIT THEREFOR Abstract In a data processing system, each bus master holds a priority code representing the bus use priority currently assigned to it. The bus master outputs the code to a bus arbitration circuit when requesting the bus. The bus arbitration circuit can be one that collectively performs the arbitration as a dedicated unit, or may be one that is distributed and held among the respective bus masters. Each bus master has a highest priority register indicating the highest priority which it can possess, a lowest priority register indicating the lowest priority, and a request priority counter indicating the priority with which it is currently provided. The counter is either incremented or decremented for each bus arbitration sequence. In a situation in which the request priority in the counter approaches the highest priority by incrementing or decrementing, the request priority is compared with the lowest priority and, when the two are equal to the lowest priority in the lowest priority register is transferred to the counter. Conversely, in a situation in which the request priority approaches the lowest priority, the request priority is compared with the lowest priority and, when the two are equal, the highest priority in the highest priority register is transferred to the counter. JA9-88-007
595248
International Business Machines Corporation
Saunders Raymond H.
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