Data processing system having centralized memory refresh

Details Data processing system having centralized memory refresh Data processing system having centralized memory refresh

G - Physics

06

F

354/230.83

G06F 9/46 (2006.01) G11C 11/406 (2006.01)

Patent

CA 1143851

ABSTRACT OF THE DISCLOSURE In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed within a predetermined time period. Logic is provided with each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.

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