Data processing system having hierarchal memories

Details Data processing system having hierarchal memories Data processing system having hierarchal memories

G - Physics

06

F

354/246

G06F 13/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1151310

A DATA PROCESSING SYSTEM HAVING HIERARCHAL MEMORIES ABSTRACT OF THE DISCLOSURE A date processing system having hierarchal memories is disclosed. The hierarchal memories are built by buffer memories contained in a plurality of central processing units, an intermediate buffer memory and a main memory having a plurality of banks. The intermediate buffer memory and the main memory are controlled under both a swap control method and a set associative control method. These two memories are accessed by an address information which includes both bank-selection address bits and set-selection address bits. The bank-selection address bits are partially modified by a part of the set-selection bits.

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