Data processing system having synchronous bus wait/retry cycle

Details Data processing system having synchronous bus wait/retry cycle Data processing system having synchronous bus wait/retry cycle

G - Physics

06

F

354/233, 340/84

G06F 13/00 (2006.01) G06F 13/12 (2006.01) G06F 13/362 (2006.01)

Patent

CA 1141866

ABSTRACT OF THE DISCLOSURE A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction, to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

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