Data processing system provided with a memory access controller

Details Data processing system provided with a memory access controller Data processing system provided with a memory access controller

G - Physics

06

F

354/239

G06F 12/10 (2006.01)

Patent

CA 1232970

PHA 1101 43 25.01.1985 ABSTRACT: Data processing system provided with a memory access controller. The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls acces thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.

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