Data processing system using a high speed data channel

Details Data processing system using a high speed data channel Data processing system using a high speed data channel

G - Physics

06

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354/239

G06F 3/00 (2006.01) G06F 11/10 (2006.01) G06F 13/10 (2006.01) G06F 13/28 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1128213

Abstract of the Disclosure A data processing system having a central processor unit (CPU) and a memory and further including a high speed, or "burst multiplexer", channel for permitting direct access to the memory by an input/output (I/O) device without the need to use registers and control signals from the central processor unit. The high speed channel utilizes its own memory port separate from that of the CPU and includes internal paths for transferring addresses and data between an I/O device and the memory. The channel further includes a memory allocation unit (MAP) which can be loaded by transfer of memory allocation data via substantially the same common path as the I/O data transfer. Appropriate control logic is also included to control the data and address transfers and the MAP load and dump operations so that blocks of data words can be transferred sequentially and directly to or from the memory.

320119

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