Data processing system with a plurality of processors...

G - Physics – 06 – F

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G06F 13/18 (2006.01) G06F 13/16 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1225749

AT9-84-011 DATA PROCESSING SYSTEM WITH A PLURALITY OF PROCESSORS ACCESSING A COMMON BUS TO INTERLEAVED STORAGE Abstract A plurality of data processor units are connect- ed to a common bus which is connected to first and second interleaved storage units. The system is a synchronous one in which timing means establish a series of information transfer intervals. One or more of the processor units contain apparatus for selectively commencing an address transfer on the bus to one of the storage units during a transfer inter- val; the storage transaction initiated by the address transfer will require more than the one transfer interval to complete. One or more of the processors have means for monitoring the bus in order to deter- mine whether an address on the bus has been trans- ferred to the first or the second storage unit during a particular transfer interval. The address transfer apparatus further includes apparatus responsive to the monitoring apparatus for selectively transferring the next subsequent address to the other of said storage units to thus achieve alternating interleav- ing between storage units.

481595

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