Data processing system with logical to physical address...

Details Data processing system with logical to physical address... Data processing system with logical to physical address...

G - Physics

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354/230.73

G06F 13/16 (2006.01) G06F 9/22 (2006.01) G06F 9/24 (2006.01) G06F 9/26 (2006.01) G06F 9/28 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1204218

ABSTRACT A data processing system having separate kernel, vertical and horizontal microcode, separate loading of vertical microcode and a permanently resident kernel microcode, and a soft console with dual levels of capability. The system includes a processor having dual ALC and microcode processors, and an instruction processor. Also included are a processor incorporating a multifunction processor memory, a malfunction nibble shifter, and a high speed look-aside memory control.

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