Data processing unit with pipelined operands

Details Data processing unit with pipelined operands Data processing unit with pipelined operands

G - Physics

06

F

354/230.87

G06F 9/38 (2006.01) G06F 9/30 (2006.01) G06F 9/318 (2006.01)

Patent

CA 1174370

ABSTRACT OF THE DISCLOSURE A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for alignning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.

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