Data processor having multiple bus cycle operand cycles

Details Data processor having multiple bus cycle operand cycles Data processor having multiple bus cycle operand cycles

G - Physics

06

F

354/231, 354/236

G06F 1/04 (2006.01) G06F 13/40 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1233265

DATA PROCESSOR HAVING MULTIPLE BUS CYCLE OPERAND CYCLES Abstract of the Disclosure In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.

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