Data receiver interface circuit

Details Data receiver interface circuit Data receiver interface circuit

H - Electricity

04

L

340/74

H04L 7/027 (2006.01) H04J 3/06 (2006.01) H04L 7/02 (2006.01)

Patent

CA 1336103

A data receiver interface circuit is provided with a circuit for accepting correctly framed data. The plurality of data bits sandwiched between a pair of frame pulses is temporarily stored while the number of clock cycles occurring between the frame pulses is determined to be a valid number. The data is accepted by the receiver if the number of clock cycles occurring between the pair of successive frame pulses is a valid number.

611329

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