G - Physics
01
R
G01R 29/18 (2006.01) G01R 25/00 (2006.01) G11B 20/10 (2006.01) G11B 20/14 (2006.01) H03L 7/091 (2006.01) H04L 7/033 (2006.01) H04L 25/06 (2006.01)
Patent
CA 2258384
An input signal is received on a digital line 10 connected to the input of a threshold slicer 60. The threshold slicer 60 provides on an output line 65 a sliced value, as is conventional, which is thereby provided to a first input of the switch 62. The threshold dicer 60 also provides a digital signal on a digital line 66 which identifies the starting state of a state machine. The starting state is determined by observing the sliced valves for two successive slicer levels which correspond to a valid succession of slicer levels, and is passed to a state logic device 63. The state logic device 63 initiates itself using the starting state received and thereafter cycles sequentially through logic states 1 to 8, corresponding to valid successions of slicer levels, with the frequency of the sampling clock. A digital value in the range 1 to 8 corresponding to the current state present in the device 63 is provided on an output line 68. The signal provided on an output line 69 of the switch 61 is, when the line 67 is at a logical 1, that provided on the output line 68 of the state logic device 63. In this way, a state to slice converter 64 is provided, after the initial state determination, with a value corresponding to the current state of the state logic device 63, and provides on its output line 70 a slice value which corresponds to a dicer level corresponding to the current state of the state logic device 63. A switch 62, after the starting state determination, provides on an output line 27 the signal received on the line 70. In this case the output of the data dicer 22 is determined by the state logic device 63.
Popplewell Andrew
Williams Stephen
Fetherstonhaugh & Co.
Lsi Logic Corporation
Mitel Semiconductor Limited
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