Dc offset calibration for a digital switching amplifier

H - Electricity – 03 – F

Patent

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Details

H03F 1/02 (2006.01) G01R 19/00 (2006.01) G06J 1/00 (2006.01) H03F 1/30 (2006.01) H03F 3/217 (2006.01) H03H 11/12 (2006.01)

Patent

CA 2380772

An offset voltage calibration circuit for use with a digital switching amplifier (400). The calibration circuit includes an analog-to-digital converter (406) for converting at least one DC offset voltage associated with the digital switching amplifier (400) to digital offset data. A memory (408) stores the digital offset data. Control circuitry (402) controls the analog-to- digital converter (406). A digital-to-analog converter (404) coupled to the memory (408) receives the digital offset data and generates an offset compensation voltage for applying to an input port of the digital switching amplifier which thereby cancels at least a portion of the at least one DC offset voltage.

L'invention concerne un circuit de calibrage de tension de décalage à utiliser avec un amplificateur (400) de commutation numérique. Ledit circuit de calibrage comprend un convertisseur analogique-numérique (406) permettant de convertir au moins une tension de décalage en continu associée à l'amplificateur (400) de commutation numérique en données de décalage numérique. Une mémoire (408) stocke les données de décalage numérique. Des circuits de commande (402) commandent le convertisseur analogique-numérique (406). Un convertisseur numérique-analogique (404) relié à la mémoire (408) reçoit les données de décalage numérique et génère une tension de compensation de décalage à appliquer à une borne d'entrée de l'amplificateur de commutation numérique qui annule ainsi au moins une partie d'une tension de décalage en continu au minimum.

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