De-glitchable non-metastable flip-flop circuit

Details De-glitchable non-metastable flip-flop circuit De-glitchable non-metastable flip-flop circuit

H - Electricity

03

K

328/129, 328/150

H03K 3/286 (2006.01) H03K 3/013 (2006.01) H03K 3/037 (2006.01)

Patent

CA 1078465

Title of the Invention DE-GLITCHABLE NON-METASTABLE FLIP-FLOP CIRCUIT Abstract of the Disclosure The flip-flop circuit of the present invention is one that cannot glitch or enter a metastable hang-up state and has a probability of one of being completely settled at some given finite time following clocking. The flip-flop circuit is com- prised of an input logic gate, an integrator and a logic latch circuit. In operation, the input logic gate changes state upon the coincidence of input signals,which change in state causes the integrator to change output level at a controlled rate. The latch circuit is sensitive to the output level of the integrator and changes state only when the integrator's output level reaches or exceeds preselected thresholds.

284138

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