De-interleaving circuit using one superframe memory storage

Details De-interleaving circuit using one superframe memory storage De-interleaving circuit using one superframe memory storage

H - Electricity

03

M

H03M 13/27 (2006.01) H04N 21/236 (2011.01) H04N 21/434 (2011.01) H04L 27/18 (2006.01) H04N 7/50 (2006.01)

Patent

CA 2337008

A de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a de-interleave memory (4) in a de- interleave order. Each main signal is read from the address location in a de- interleave memory (4) specified by address data (A), and the following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory (4) only requires space for one superframe.

L'invention concerne un circuit de désentrelacement avec une mémoire inférieure. Un générateur de données adresses (3) fournit des données adresses (A) à une mémoire de désentrelacement (4) dans un ordre de désentrelacement. Chaque signal principal est lu depuis l'emplacement d'adresse situé dans une mémoire de désentrelacement (4) et spécifié par lesdites données adresses (A), le signal principal suivant étant désentrelacé puis écrit dans cet emplacement d'adresse de la mémoire. La mémoire de désentrelacement (4) susmentionnée ne nécessite donc que l'espace d'une supertrame.

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