Debounce circuit providing synchronously clocked digital...

H - Electricity – 03 – K

Patent

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328/126

H03K 5/01 (2006.01) H03K 5/1252 (2006.01) H03K 17/16 (2006.01)

Patent

CA 1210827

Abstract Debounce Circuit Providing Synchronously Clocked digital Signals An improved debouncer circuit is disclosed for providing debounced, synchronously clocked digital signals from a single-throw switch, as for instance, of the momentary contact type. A signal, variable between two logic levels, is provided by the switch for input to the debouncer circuitry. that input signal is applied as one input to an EXCLUSIVE OR gate, the other input to that gate being fed back from the Q output terminal of an output data latch having complementary Q and Q* output terminals. The Q* output terminal of the data latch is connected to the D input of that latch such that a synchronous clocking signal appearing at the clock input of the data latch serves to toggle the states of the Q and Q* output terminals. The signal appearing at either one of the output terminals Q, Q* of the output data latch may be used as the debouced signal provided to other circuitry, depending upon signal polarity needs.

463854

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