Debugging port security interface

Details Debugging port security interface Debugging port security interface

G - Physics

06

F

G06F 12/14 (2006.01) G06F 11/36 (2006.01)

Patent

CA 2536610

The present invention provides a secure JTAG interface to an application- specific integrated circuit (ASIC). In the preferred embodiment the invention operates through the combined efforts of a Security Module (SM) comprising a state machine that controls the security modes for the ASIC, and a Test Control Module (TCM) which contains the JTAG interface. The TCM operates in either a restricted mode or an unrestricted mode, depending on the state of the SM state machine. In a restricted mode, only limited access to memory content is permitted. In an unrestricted mode, full access to memory content is permitted.

L'invention concerne une interface JTAG sécurisée vers un circuit intégré spécifique (ASIC). Dans le mode réalisation préféré, l'invention concerne les efforts combinés d'un module de sécurité (SM) comprenant une machine d'état qui commande les modes de sécurité de l'ASIC, et un module de commande d'essai (TCM) qui renferme l'interface JTAG. Le TCM fonctionne en mode réservé ou en mode libre, en fonction de l'état de la machine d'état du SM. En mode réservé, seul un accès limité au contenu de la mémoire est autorisé. En mode libre, l'accès total au contenu de la mémoire est autorisé.

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