Decoder circuit

Details Decoder circuit Decoder circuit

G - Physics

11

C

354/111, 352/81

G11C 11/40 (2006.01) G11C 8/10 (2006.01) G11C 8/12 (2006.01) G11C 11/415 (2006.01) H03M 7/00 (2006.01)

Patent

CA 1150838

- 18 - DECODER CIRCUIT ABSTRACT OF THE DISCLOSURE A decoder circuit which receives a plurality of address signals and selects one of the n x m word lines for driving a semiconductor memory device, comprising; a high level selection circuit which receives the upper address signals and produces n outputs, one of the n outputs is selected to be a high level, while the other (n-1) outputs are rendered at a low level; a low level selection circuit which receives the lower address signals and produces m outputs, one of the m outputs is selected to be the low level, while the other (m-1) outputs are rendered at the high level, and; n x m coupling circuits each of which receives one outputs from the high level selection circuit and one output from the low level selection circuit and which corresponds to one of the n x m word lines. Each of the coupling circuit selects the corresponding word line when the high level output from the high level selection circuit and the low level output from the low level selection circuit are simultaneously applied to the coupling circuit.

370290

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