Decoder circuit

Details Decoder circuit Decoder circuit

H - Electricity

03

K

328/188, 328/92

H03K 19/20 (2006.01) G11C 8/08 (2006.01) G11C 8/10 (2006.01) G11C 8/18 (2006.01) G11C 11/408 (2006.01) H03K 19/08 (2006.01) H03M 7/00 (2006.01)

Patent

CA 1167117

ABSTRACT In a decoder circuit in which a transistor for power reducing use, which is supplied at its gate with a first control signal, is connected in series with a logical gate composed of a load transistor and a plurality of transistors which are respectively supplied at their gates with address signals, there is provided an off buffer circuit which com- prises a first inverter for receiving the output from the logical gate and a second inverter for receiving the output from the first inverter. To a load transistor of the second inverter is provided a second control signal delayed in phase behind the first control signal and the output from the off buffer circuit is used as a decoded output of the address signal.

365063

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