Decoder circuit for semiconductor memory

Details Decoder circuit for semiconductor memory Decoder circuit for semiconductor memory

G - Physics

11

C

352/41

G11C 11/34 (2006.01) G11C 8/10 (2006.01)

Patent

CA 1169964

DECODER CIRCUIT FOR SEMICONDUCTOR MEMORY ABSTRACT OF THE DISCLOSURE A decoder circuit (66) includes a plurality of input transistors (78-86) connected to address lines (68-76). The drain terminals of the input transistors (78-86) are connected to a first power terminal and the source terminals thereof are connected to a first node (92) which is charged to low voltage state upon receipt of a precharge signal at a transistor (94). An address enable signal (58) operates a transistor (96) to connect node (92) to node (98) during receipt of the address. A node (102) is charged to a high state by operation of a transistor (100) in response to a precharge signal (56). Node (102) is discharged through a transistor (104) when a high voltage state is present at the node (98). An enable clock signal (52) is transmitted through a transistor (106) to a row line (108) when a high voltage state is present on node (102).

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