Decoder having a true and a complement output

H - Electricity – 03 – M

Patent

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354/67

H03M 7/22 (2006.01)

Patent

CA 1129101

DECODER HAVING A TRUE AND A COMPLEMENT OUTPUT Abstract A digital decoder for use with a dual bus system is provided having a minimum number of transistors. The decoder is easily expandable to decode larger binary coded input signals. As a minimum only six transistors are needed to decode a three-bit binary input signal to provide outputs for a data bus and its complement. By using a minimum number of transistors, less current is required for the decoder. The circuitry used to provide each decoded output is repeated in a manner which conserves silicon area when the decoder is placed on silicon. A minimum number of control lines are used.

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