Decoding apparatus and method for d.c. free data...

H - Electricity – 03 – K

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340/165

H03K 13/00 (1980.01)

Patent

CA 1090899

ABSTRACT A method and apparatus for decoding transmitted binary data in which net DC components have been suppressed. The data is transmitted in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by producing a first indicating signal, and in response to the first indicating signal, the state of a current bit and the state of the next succeeding bit, the transmission of signal transitions is modified to eliminate any DC component. The decoding apparatus includes a synchronizer responsive to transmitted signal transitions for providing timing signals for distinguishing relatively early transitions from relatively late transitions and a detector responsive to transmitted signal transitions and the timing signals for indicating first bit states upon receipt of relatively early transitions and second bit states upon receipt of relatively late transitions. A Abstract...continued. suppressed transition detector is responsive to transmitted signal transitions and the timing signals for detecting the absence of a transition for an interval corresponding to 2 1/2 bit cells following a relatively late transition by producing a suppressed transition detection signal.

344075

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