Decoding tim bus structure

Details Decoding tim bus structure Decoding tim bus structure

H - Electricity

04

J

363/10

H04J 3/02 (2006.01) H04B 7/212 (2006.01) H04L 5/22 (2006.01)

Patent

CA 1155977

DECODING TIM BUS STRUCTURE ABSTRACT A multiplexing/demultiplexing bus structure employing a mapping RAM in common equipment and a decoding device in a plurality of interface modules. The common equipment provides identical encoded information to each of the decoders in the interface modules, the decoders in each of the interface modules determining whether or not incoming or outgoing data is to be written into or read from the associated interface module. The decoders initiate a count to provide an address for the data written into or read out of a buffer in the associated interface module. The common equipment can thereby provide burst-to-burst selection of data. Burst and/or channel allocation may be changed in real time for any of the interface modules through a "demand assignment" process. A central network controller receives all capacity and destination requests for processing. The controller can then send capacity and destination assign- ments to network stations where they are received and decoded. The mapping functions of the appropriate RAMs are updated in accordance with the central network con- troller's instructions.

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