Decoding unit and preprocessing unit implemented according...

Details Decoding unit and preprocessing unit implemented according... Decoding unit and preprocessing unit implemented according...

H - Electricity

03

M

H03M 13/00 (2006.01) H03M 13/03 (2006.01) H03M 13/09 (2006.01) H03M 13/19 (2006.01) H04L 1/00 (2006.01)

Patent

CA 2499177

In processing of calculating outer value log-ratio .alpha.mn by a row processing unit performing an operation on rows of a parity check matrix, a minimum absolute value and a second minimum absolute value out of data utilized for the row processing are stored. When the data to be processed matches with the minimum value, the second minimum value is outputted. When the data to be processed does not match with the minimum value, the minimum value is output. Thus, it is possible to simplify a construction of a portion for executing Min operation of obtaining a minimum value in the processing of a decoding operation according to a min-sum decoding algorithm. It is possible to reduce a scale of circuitry for decoding low density parity check codes.

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