Delay logic for preventing cpu lockout from bus ownership

Details Delay logic for preventing cpu lockout from bus ownership Delay logic for preventing cpu lockout from bus ownership

G - Physics

06

F

354/234

G06F 13/14 (2006.01) G06F 13/362 (2006.01)

Patent

CA 2021826

BC9-89-044 ABSTRACT A logic controlled delay circuit is connected into the arbitration logic of a computer system of the type having a main data bus which is subject to control by multiple masters. The delay is so programmed that the default master, which is the main processor (CPU) for the system and is assigned the residual or default priority, is assured a predefined portion of the time available on the bus. By so inserting and controlling the delay that the "hold" signal to the CPU is delayed whenever the CPU is granted access to the bus, other devices, are unable to seize the bus until the delay has ended at which time the CPU is triggered by the delayed signal to respond with an acknowledge which serves to permit arbitration to begin. By this technique a standard microprocessor such as an Intel 80386 can operate in such an architecture without being preempted from the bus by the higher priority devices to an extent that system operation deteriorates.

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