Delayed cache write enable circuit for a dual bus...

Details Delayed cache write enable circuit for a dual bus... Delayed cache write enable circuit for a dual bus...

G - Physics

06

F

354/241, 354/230

G06F 13/16 (2006.01) G06F 12/08 (2006.01) G06F 13/38 (2006.01)

Patent

CA 1314103

BC388-G06 DELAYED CACHE WRITE ENABLE CIRCUIT FOR A DUAL BUS MICROCOMPUTER SYSTEM WITH AN 80386 AND 82385 ABSTRACT In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cacne memory components and at the same time does not impact wait state parameters for read miss operations.

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