Demodulation device for multiphase psk or multilevel qam...

H - Electricity – 03 – D

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H03D 3/18 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1240001

Abstract of the Disclosure In a demodulation circuit, a timing synchronizing circuit generates a timing signal representing a sampling timing of an A/D converter and has a timing signal generator, a polarity identification circuit and a logic circuit. The timing signal generator is phase-controlled by a phase control signal and generates a timing signal. The polarity identification circuit identifies a polarity of a differential coefficient of the baseband signal at a sampling point of the A/D converter and generates a polarity identification signal. Upon logic processing, the logic circuit supplies to the timing signal generator the phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point. A carrier asynchronism detection circuit detects an asynchronism state of a carrier regenerating circuit and supplies to the timing synchronizing circuit a signal which changes its loop parameter.

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