Demultiplexer for a serial and isochronous multiplex signal

Details Demultiplexer for a serial and isochronous multiplex signal Demultiplexer for a serial and isochronous multiplex signal

H - Electricity

04

J

363/10

H04J 3/02 (2006.01) H04J 3/04 (2006.01) H04J 3/16 (2006.01)

Patent

CA 2011283

PHD 89.038 20.2.1990 ABSTRACT Demultiplexer for a serial and isochronous multiplex signal The described demultiplexer is intended for a serial and isochronous multiplex signal consisting of Q isochronous tributary signals interleaved bock-by-block, each block containing K bits. An associated multiplexer is also described. In order to keep the required memory capacity in a demultiplexer as small as possible, a write/read memory (5) is utilized, into which the bits of the multiplex signal are cyclically written and from which, simultaneously, the bits of the tributary signals are read out cyclically. A write/read control (4) coordinates the writing and reading processes in a manner such that no collisions occur. In an exemplary embodiment the bits of the multiplex signal are written into the write/read memory (5) bit-by-bit by means of a serial-to-parallel converter (2). Reading is effected bit-by-bit while utilizing read logics (81, 82, 83, 84) which are also controlled by the write/read control (4) via addresses. At the output (91, 92, 93, 94) of each of these read logics (81, 82, 83, 84) the tributary signals are available in a serial form.

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