Device and method for limiting delay by substantial...

Details Device and method for limiting delay by substantial... Device and method for limiting delay by substantial...

H - Electricity

04

L

H04L 29/02 (2006.01) H03M 7/30 (2006.01) H04J 3/06 (2006.01) H04J 3/14 (2006.01) H04L 1/18 (2006.01)

Patent

CA 2159110

The method (100, 200) and data communication equipment (300, 400) utilizing the method to substantially eliminate duplicate synchronous data frames thus limiting delay for a synchronous data system having error correcting protocol. Duplicate synchronous data frames are eliminated for timeouts where a communication channel becomes unusable for timeout that exceeds a preselected value.

Procédé (100,200) et équipement de communication de données (300,400), ledit procédé étant mis en oeurvre pour éliminer pratiquement totalement les blocs d'informations synchrones en double, et limiter ainsi le retard pour un système de données synchrones doté d'un protocole de correction d'erreurs. Les blocs d'information synchrones en double sont éliminés de manière à limiter les délais d'attente dépassant une valeur présélectionnée, pendant lesquels une voie de communication devient inutilisable.

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