Device and method for normalizing metric value of component...

Details Device and method for normalizing metric value of component... Device and method for normalizing metric value of component...

H - Electricity

04

B

H04B 1/69 (2006.01) H03M 13/29 (2006.01) H03M 13/41 (2006.01) H03M 13/45 (2006.01)

Patent

CA 2354466

A decoder using transition of a plurality of metric values at a plurality of time durations is disclosed. The decoder comprises a decision circuit that generates a decision signal when the metric values all exceed a predetermined value. A subtracter subtracts the predetermined value from the metric values in response to the decision signal so as to normalize the metric values. The decision circuit includes a plurality of memories having a predetermined number of bits that store the corresponding metric values. A NAND gate NANDs the most significant bit (MSB) values provided from the respective memories. The NAND gate generates the decision signal that initiates resetting of the MSB values of the respective memories, when the MSB values are all HIGH or "1".

L'invention concerne un décodeur utilisant la transition de plusieurs unités métriques sur plusieurs intervalles de temps. Le décodeur comprend un circuit de décision qui fournit un signal de décision lorsque les unités métriques dépassent toutes une valeur préétablie. Une unité soustractive soustrait ladite valeur des unités métriques, d'après le signal de décision, afin de normaliser les unités métriques. Le circuit de décision comprend plusieurs mémoires comportant un nombre de bits préétabli, qui enregistrent les unités métriques correspondantes. Une porte NON-ET traite les valeurs du bit de poids fort fournies par les mémoires respectives. Cette porte fournit le signal de décision qui réinitialise les valeurs du bit de poids fort des mémoires respectives, lorsque les valeurs de ce bit sont toutes au niveau ELEVE ou "1".

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