Device and pixel architecture for high resolution digital...

Details Device and pixel architecture for high resolution digital... Device and pixel architecture for high resolution digital...

H - Electricity

01

L

H01L 31/10 (2006.01) H04N 3/15 (2006.01) H04N 5/335 (2006.01)

Patent

CA 2639498

The present invention discloses structure of a two-gate field effect transistor (FET), named as charge gated FET, and presents various active pixel sensor (APS) and multimode architectures using the device which has only one, or two on-pixel transistors for high resolution, high gain and fast frame rate APS arrays. It is also disclosed a new method of addressing pixels of an APS array by applying the addressing voltage pulse directly to the gate of the amplifying transistor of the pixel architecture, eliminating the row select transistor from the pixel circuit.

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