Device for reducing the redundancy in blocks of digital...

H - Electricity – 04 – N

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H04N 7/12 (2006.01) G06T 9/00 (2006.01) H04N 7/30 (2006.01) H04N 7/50 (2006.01)

Patent

CA 2012747

ABSTRACT A converter processes a digital video signal according to a known redundancy reducing algorithm executed on successive block for each frame or field, generating a transformed signal which is applied to a quantizer adapted to generate a quantized signal at preset transition levels on opposed sides of the zero, including the zero (...,-3,-2,-1 0, 1, 2, 3,...). The quantized signal is processed by a processor, adapted to determine the block length and the consecutive zero sequences along a preset scanning order, and to output a symbolic signal constituted by symbols indicating the quanti- zation levels of the non null data, the zero sequences and a symbol indicating the block end. The symbolic signal is applied to a variable length VLC encoder, adapted to encode data according to a preset designation law for generating a signal which is applied to a transmission buffer. According to the invention, said quantized signal, generated by the quantizer, further includes two ambiguous levels (x1 and x-1) at input values falling within respective preset intermediate ranges respectively between the zero level and the first positive level and between the zero level and the first negative level; the processor transforms each of the ambi- guous levels respectively in a first positive level and first negative level if the preceding and subsequent input values are both non null and non ambiguous, and transforms the ambiguous level in zero level in all the other cases.

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