Device for timing reconstruction of a data channel...

Details Device for timing reconstruction of a data channel... Device for timing reconstruction of a data channel...

H - Electricity

04

L

H04L 7/033 (2006.01) H04J 3/06 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2312114

A memory (2) for data accumulation includes an input (3) on which such data are entered as a stream of input data (Pin) under the control of an input timing signal (xIN), and an output (4) starting from which the data entered in memory (2) are read as a stream of output data (Pout) under the control of a reconstructed timing signal (XOUT). A phase-locked loop (7) uses this input timing signal (xIN) as an input signal to generate a corresponding phase-locked output signal (xOUT). The reconstructed timing signal is obtained starting from the output signal of such phase-locked loop output (7). Means (8) are provided to measure residual phase wander and act (23, 9, 10) on the transfer function band of the phase of phase-locked loop output (7), which is preferable without ring filters (Figure 1).

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