Di-phase pulse receiving system

H - Electricity – 03 – K

Patent

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354/105

H03K 5/156 (2006.01) H03K 5/15 (2006.01) H04L 25/45 (2006.01)

Patent

CA 1111965

DI-PHASE PULSE RECEIVING SYSTEM ABSTRACT OF THE DISCLOSURE The disclosure relates to a control means for converting serially transmitted di-phase logic bits into parallel data bits having corresponding discrete logic levels. The control means of the present invention is adapted for use in a di-phase pulse receiving system of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di- phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion. The control means comprises a first set means coupled to the positive peak detector and responsive to the first pulses for being set upon the detection of a positive di-phase signal portion, a second set means coupled to the negative peak detector and responsive to the second pulses for being set upon the detection of a negative di-phase signal portion, and a shift register means having a first input coupled to the first set means, a second input coupled to the second set means, a clock input coupled to the positive detector for being clocked by the trailing edge of the first pulses, and a plurality of parallel outputs. The shift register means is responsive to the coincidence of the first and second set means being set upon being clocked to thereby shift a first logic level to the parallel output and is responsive to only the first set means being set upon being clocked to thereby shift a second logic level to the parallel output.

293236

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