Diagnostic-debug machine architecture

Details Diagnostic-debug machine architecture Diagnostic-debug machine architecture

G - Physics

06

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354/225

G06F 11/00 (2006.01) G01R 31/317 (2006.01) G01R 31/3185 (2006.01) G06F 11/36 (2006.01) G06F 11/267 (2006.01)

Patent

CA 1148264

A DIAGNOSTIC/DEBUG MACHINE ARCHITECTURE Abstract A system is described for enabling the connection of a diagnostic/debugging processor to another host processor for the purpose of troubleshooting that processor's hardware and software. The system is composed of an interface between the diagnostic/ debugging processor per se and the host processor to be diagnosed, and of software resident in the diagnostic processor to perform functions required by the user of the system. The system is specif- ically designed for use with a host processor utilizing LSSD design rules. YO978-048

363526

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