Digital adder circuitry

Details Digital adder circuitry Digital adder circuitry

G - Physics

06

F

354/209

G06F 7/50 (2006.01)

Patent

CA 1191961

- 13- ABSTRACT OF THE DISCLOSURE Circuitry for generating a carry signal from a binary adder stage is described. The adder stage has terminals for a carry input, and two binary digit inputs. The carry signal is generated at a carry output terminal. A first switch means connects the carry input terminal to the carry output terminal when the two binary digit inputs are at different logic levels. Two serially coupled transistors are coupled between the carry output terminal and a source of positive supply potential, and have their control electrodes coupled to respective binary digit inputs. Two further serially coupled transistors are coupled between the carry output terminal and a source of negative supply potential, and have their control electrodes coupled to respective binary input digits.

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