Digital arithmetic circuit

G - Physics – 06 – F

Patent

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Details

G06F 11/14 (2006.01) G06F 7/544 (2006.01) G06F 11/16 (2006.01) G06F 7/00 (2006.01)

Patent

CA 2200715

A digital arithmetic circuit (10) includes an inverting circuit (28) connected to a digital circuit (48) in which errors are to be detected. An operand input to the circuit (10) produces an output result in a first operation which is stored in a comparison circuit (82). The operand is inverted by the inverting circuit (28) on a second cycle of operation of the circuit (10) and the output result is compared by the comparison circuit (82) with that from the first operation. A non-zero result from the comparison indicates the occurrence of an error or errors in the operation of the circuit (10).

Circuit arithmétique numérique (10) comprenant un circuit (28) inverseur raccordé à un circuit (48) numérique dans lequel les erreurs doivent être détectées. Une valeur d'entrée d'opérande dans le circuit (10) produit un résultat de sortie dans une première opération, lequel est mémorisé dans un circuit (82) de comparaison. L'opérande est inversé par le circuit (28) inverseur au cours d'un second cycle d'opération du circuit (10) et le résultat de sortie est comparé par le circuit (82) de comparaison avec le résultat de sortie de la première opération. Un résultat non nul provenant de la comparaison indique la survenue d'une erreur ou d'erreurs dans l'opération du circuit (10).

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